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Re: exception priority for BCM1250

To: linux-mips@linux-mips.org
Subject: Re: exception priority for BCM1250
From: "Lijun Chen" <chenli@nortelnetworks.com>
Date: Wed, 31 Mar 2004 10:39:19 -0500
Cc: Dominic Sweetman <dom@mips.com>, ralf@linux-mips.org
Organization: Nortel Networks
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Thanks a lot, Dominic and Ralf.
So interrupts and a few exception conditions are maskable and preemptable.
The machine-level exceptions are non-maskable.If ever multiple exceptions occur
at the same time, cpu picks the highest priority one.

But in the MIPS64 spec, it says the EXL bit is set when any exception other than Reset, Soft reset, NMI or Cache Error exception are taken. Does this mean Cache error can
preempt whatever else is going on except for Reset and NMI?

My intention is to write some information to a kernel buffer when cache and bus error exceptions occur. If they use the common buffer and a spin_lock() is used before writing, will this cause dead lock if kernel is handling bus error while a cache error
occurs?

Thanks again.
Lijun

Dominic Sweetman wrote:

Lijun,

Does anybody know which mips family SB1 core on bcm1250 falls into?
It is a MIPS64 processor

Yes, it complies to the MIPS64 Architecture specification...

... does it belong to 5K family or 20Kc?

Neither one.  5K and 20Kc are specific core CPUs licensed by MIPS
Technologies.  Broadcom have an "architecture license" and design
their own compatible MIPS64 CPUs, like the BCM1250.

What about the exception priorities, such as cache error exception,
bus error exception, and so on? Are they maskable or non-maskable?

Other than interrupts, only a few obscure exception conditions are
maskable.
Ralf was sensible to suggest you back off to the architecture manuals,
which talk about all MIPS CPUs.  You might also like to read a book
(like my "See MIPS Run").

Further to my last email, another question is if multiple
simultaneous exceptions occur, or kernel is handling an exception,
another exception occurs, how linux handles this?

As always, that depends what you mean by "handling".

At the lowest level, the CPU:

o If ever confronted by multiple possible exceptions at the same time,
 picks the highest priority one which affects the oldest instruction
 in the pipeline...

o When it takes the exception and vectors into the kernel exception
 handler, it atomically sets the register bit SR[EXL] ("exception
 mode").  In this mode interrupts are disabled.  The kernel code
 should be careful not to cause an exception.

Read the book, is my advice.

Of course Linux goes on from the low-level exception handler to call
other kernel functions which you might regard as "handlers" too -
interrupt routines, for example.  In many cases these OS "handlers"
are run with SR[EXL] set to zero, making it possible to handle new
machine-level exceptions...
But that's complicated.

--
Dominic Sweetman
MIPS Technologies






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