linux-mips
[Top] [All Lists]

Re: exception priority for BCM1250

To: Lijun Chen <chenli@nortelnetworks.com>
Subject: Re: exception priority for BCM1250
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 31 Mar 2004 01:43:42 +0200
Cc: linux-mips@linux-mips.org
In-reply-to: <4069F90D.9060903@americasm01.nt.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4069F90D.9060903@americasm01.nt.com>
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.4.1i
On Tue, Mar 30, 2004 at 05:47:41PM -0500, Lijun Chen wrote:

> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor, does it belong to 5K family or 20Kc?

They're all MIPS64.

> What about the exception priorities, such as cache error exception, bus 
> error exception, and so on? Are they maskable or non-maskable? It is not
> clear from BCM1250 and sb1 core manuals.

This is explained in the MIPS64 spec.

  Ralf

<Prev in Thread] Current Thread [Next in Thread>