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Re: exception priority for BCM1250

To: linux-mips@linux-mips.org
Subject: Re: exception priority for BCM1250
From: "Lijun Chen" <chenli@nortelnetworks.com>
Date: Tue, 30 Mar 2004 18:38:02 -0500
Cc: "Lijun Chen" <chenli@nortelnetworks.com>
Organization: Nortel Networks
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <4069F90D.9060903@americasm01.nt.com>
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Further to my last email, another question is if multiple simultaneous exceptions occur, or kernel is
handling an exception, another exception occurs, how linux handles this?

Thanks,
Lijun

Chen, Lijun [CAR:7Q28:EXCH] wrote:

Hi,

Does anybody know which mips family SB1 core on bcm1250 falls into?
It is a MIPS64 processor, does it belong to 5K family or 20Kc?

What about the exception priorities, such as cache error exception, bus error exception, and so on? Are they maskable or non-maskable? It is not clear from
BCM1250 and sb1 core manuals.

Thanks a lot.

Lijun






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