Re: exception priority for BCM1250

["Lijun Chen" <chenli@nortelnetworks.com>]

Further to my last email, another question is if multiple simultaneous 
exceptions occur, or kernel is
handling an exception, another exception occurs, how linux handles this?

Thanks,
Lijun

Chen, Lijun [CAR:7Q28:EXCH] wrote:

> Hi,
>
> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor, does it belong to 5K family or 20Kc?
>
> What about the exception priorities, such as cache error exception, 
> bus error
> exception, and so on? Are they maskable or non-maskable? It is not 
> clear from
> BCM1250 and sb1 core manuals.
>
> Thanks a lot.
>
> Lijun