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Re: missing flush_dcache_page call in 2.4 kernel

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: missing flush_dcache_page call in 2.4 kernel
From: Peter Horton <phorton@bitbox.co.uk>
Date: Tue, 30 Mar 2004 10:48:42 +0100
Cc: pdh@colonel-panic.org, linux-mips@linux-mips.org
In-reply-to: <20040330.153842.48794669.nemoto@toshiba-tops.co.jp>
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References: <20040326184317.GA3661@skeleton-jack> <20040327.224952.74755860.anemo@mba.ocn.ne.jp> <20040328130400.GA28177@skeleton-jack> <20040330.153842.48794669.nemoto@toshiba-tops.co.jp>
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Atsushi Nemoto wrote:

On Sun, 28 Mar 2004 14:04:00 +0100, Peter Horton <pdh@colonel-panic.org> said:
pdh> I've ditched the original Cobalt hack in c-r4k.c, and am using
pdh> the patch below instead. Seems to work okay ...

+       for (; addr < (void *) end; addr += PAGE_SIZE)
+               flush_data_cache_page((unsigned long) addr);

dma_cache_wback() will be more efficient ?
Well technically it should be dma_cache_wback_inv(), though they equate to the same function currently.

It would be more efficient, but the dma_cache_*() functions are only available under CONFIG_DMA_NONCOHERENT, and our problem has nothing to do with DMA coherency at all.

All we really need to do is add a flush_dcache_range(from,to) function. I'm working on this at the moment.

Also, I personally think replacing all insb/insw/insl is a bit
overkill.  I'd prefer redefine insb/insw/insl in asm-mips/ide.h, but
I'm not sure it is enough. (really all ins[bwl] should take care of
the cache inconsistency?)

There maybe other block drivers (SCSI?) that use insb/insw/insl that would also cause us grief, but we could provide both versions of the functions and select them as necessary.

P.

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