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Re: BUG in pcnet32.c?

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: BUG in pcnet32.c?
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 30 Mar 2004 03:24:03 +0200
Cc: "Steven J. Hill" <sjhill@realitydiluted.com>, Brian Murphy <brian@murphy.dk>, linux-mips@linux-mips.org
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On Mon, Mar 29, 2004 at 10:55:52PM +0200, Kevin D. Kissell wrote:

> Which reminds me of something I've been meaning to mention for a while.
> Back in the dark days of Linux 2.2 on MIPS, I discovered that a number
> of network drivers were subtly broken for MIPS because they allocated
> enough extra space for IP header alignment, but not for cache line alignment.
> Particularly on CPUs with write-back caches, it can be a Bad Thing if a cache 
> line straddles two packet buffers, as the flush of one can cause the other
> to be clobbered.  I had to redefine the alignment constant for MIPS to be
> a function of the line size to have 100% solid operation of the Tulip and
> pcnet32 drivers.
> 
> The whole network driver cache management paradigm was redone for 2.4,
> and I've often wondered whether the same potential problem exists, but never
> had the time to go in and check.

The change goes beyond just cache managment; the API also abstracts away
I/O MMUs which so far are quite rare on MIPS systems - but I really hope
they're going to establish themselves asap.

The Documentation/DMA-API.txt also documents how properly deal with cache
alignment when using this API.

Steven, maybe that we should add another assertion to make sure we don't
run into trouble with missaligned cachelines?

> There, I've mentioned it.  My conscience is clear.  ;o)

Ommmmm ;))

  Ralf

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