"ashish anand" <email@example.com> writes:
> I am restarting a thread discussed november last year regarding
> spurious interrupts generation due to edge triggering .
> pls. refer ,
> somehow this problem is again surfaced.
> I am interfacing a peripheral to mips CP0 interrupt controller
> through GPIO which converts edge to level .
> now my question is that ,
> is it always safe to clear the interrupt status outside the interrupt handler
> in a driver under some particular path flow ?
> I think it is not as it may land-up in a situation where by the time
> GPIO detects the edge due to requirement of certain minimum pulse width
> duration , it is already cleared and thus a spurious interrupt generation
> will happen.
> I might be wrong .I am looking for comments on above mentioned situation.
> Best Regards,
I might be wrong, I'm just starting learing about the details of mips,
but its my understanding that the interrupt would reassert itself
imediatly when you leave the interrupt vector without clearing it
That said, when you are outside the interrupt handler the interrupt
bit should always be unset. The only thing I can imagine hapening is
the interrupt getting triggered while the clear instruction is
running. You might or might not have a race condition there then.
But why would you ever want to clear an interrupt outside the handler,
it normaly cannot be set. Spurious interrupts shouldn't be caused by
this I think. If at all you would miss some interrupt completly.
Or am I totally off there?