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clearing interrupt outside handler..?

To: linux-mips@linux-mips.org
Subject: clearing interrupt outside handler..?
From: "ashish anand" <ashish_ibm@rediffmail.com>
Date: 26 Mar 2004 13:06:00 -0000
Original-recipient: rfc822;linux-mips@linux-mips.org
Reply-to: "ashish anand" <ashish_ibm@rediffmail.com>
Sender: linux-mips-bounce@linux-mips.org
Hello,

I am restarting a thread discussed november last year regarding
spurious interrupts generation due to edge triggering .
pls. refer ,
http://www.linux-mips.org/archives/linux-mips/2003-11/msg00071.html

somehow this problem is again surfaced.
I am interfacing a peripheral to mips CP0 interrupt controller
through GPIO which converts edge to level .
now my question is that ,

is it always safe to clear the interrupt status outside the interrupt handler 
in a driver under some particular path flow ?
I think it is not as it may land-up in a situation where by the time
GPIO detects the edge due to requirement of certain  minimum pulse width 
duration , it is already cleared and thus a spurious interrupt generation will 
happen.

I might be wrong .I am looking for comments on above mentioned situation.

Best Regards,
Ashish



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