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Re: gcc support of mips32 release 2

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: gcc support of mips32 release 2
From: Michael Uhler <uhler@mips.com>
Date: 22 Mar 2004 08:19:38 -0800
Cc: Dominic Sweetman <dom@mips.com>, Eric Christopher <echristo@redhat.com>, Long Li <long21st@yahoo.com>, linux-mips@linux-mips.org, David Ung <davidu@mips.com>, Nigel Stephens <nigel@mips.com>
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The real issue is one of strictly nested interrupts.  The lack of an
atomic di, in particular, works fine as long as all interrupts are
strictly nested in such a way that no interrupt code changes the
state of the IM bits between the read and write of the sequence.
While most operating systems appear to be strictly nested, there
are some very important kernels in embedded markets which are not
strictly nested.

When I added di (and, for symmetry, ei) to Release 2, I did so after
spending considerable time talking with these customers and was
convinced that it was important.

/gmu

On Mon, 2004-03-22 at 03:14, Maciej W. Rozycki wrote:

> > The 'di' is there to be atomic.  Such sequences are rare and code
> > compactness is not an issue.  As you probably heard before, the use of
> > a potentially-interruptible RMW sequence on the status register to
> > disable interrupts is potentially troublesome (most common OS' manage
> > themselves so it isn't an issue, but still...)
> 
>  Hmm, is the remaining minority of the OSes, that can't manage the
> sequence, important enough to add such an instruction?  The atomicity of
> this operation should only matter if interrupt handlers are expected to
> leave interrupts disabled upon an exit to the same context -- such a setup
> should be pretty rare.

-- 
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.  Email: uhler@mips.com
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