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Re: gcc support of mips32 release 2

To: Dominic Sweetman <dom@mips.com>
Subject: Re: gcc support of mips32 release 2
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Mon, 22 Mar 2004 12:14:24 +0100 (CET)
Cc: Eric Christopher <echristo@redhat.com>, Long Li <long21st@yahoo.com>, linux-mips@linux-mips.org, David Ung <davidu@mips.com>, Nigel Stephens <nigel@mips.com>
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Organization: Technical University of Gdansk
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Dominic,

> But an important sub-class of embedded workloads are data intensive,
> where the data represents some sort of stream.  Basic data items are
> often 8- or 16-bits in size.  Existing RISC instruction sets end up
> bloating the inner loops of these programs, and it's marginal
> performance gains rather than code size which motivates us to make
> this work better.

 I see.  Though the associated code compaction reduces cache footprint
which improves performance as well.

> The 'di' is there to be atomic.  Such sequences are rare and code
> compactness is not an issue.  As you probably heard before, the use of
> a potentially-interruptible RMW sequence on the status register to
> disable interrupts is potentially troublesome (most common OS' manage
> themselves so it isn't an issue, but still...)

 Hmm, is the remaining minority of the OSes, that can't manage the
sequence, important enough to add such an instruction?  The atomicity of
this operation should only matter if interrupt handlers are expected to
leave interrupts disabled upon an exit to the same context -- such a setup
should be pretty rare.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

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