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SB1250 Pass1 Cache Workaround

To: "'linux-mips@linux-mips.org'" <linux-mips@linux-mips.org>
Subject: SB1250 Pass1 Cache Workaround
From: Lance Richardson <lrichardson@extremenetworks.com>
Date: Wed, 11 Feb 2004 14:50:06 -0800
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
A recent change to arch/mips/mm/cex-sb1.S dropped the workaround 
for the SB1250 pass 1 spurious cache exception problem (yes, some
of us still have SWARMs with pass 1 parts...)

Here's a patch to restore the workaround, tested/verified on a 
SWARM with pass1 SB1250. It also removes the #include <asm/processor.h> 
which (as pointed out recently) causes grief for the assembler.

  - Lance

===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/cex-sb1.S,v
retrieving revision 1.13
diff -u -r1.13 cex-sb1.S
--- cex-sb1.S   14 Jan 2004 18:46:21 -0000      1.13
+++ cex-sb1.S   10 Feb 2004 17:30:08 -0000
@@ -23,7 +23,6 @@
 #include <asm/mipsregs.h>
 #include <asm/stackframe.h>
 #include <asm/cacheops.h>
-#include <asm/processor.h>
 #include <asm/sibyte/board.h>
 
 #define C0_ERRCTL     $26             /* CP0: Error info */
@@ -83,6 +82,19 @@
         mtc0   $0,C0_CERR_D
 
 attempt_recovery:
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+       # look for signature of spurious CErr
+       lui     k0, 0x4000
+       bne     k0, k1, 1f
+        mfc0   k1, C0_CERR_I, 1
+       lui     k0, 0xffe0
+       and     k1, k0, k1
+       lui     k0, 0x0200
+       beq     k0, k1, recovered 
+        mtc0   $0,C0_CERR_D
+1:
+#endif
+
        /*
         * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31.  Any
         * Dcache errors we can recover from will take more extensive


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