| To: | Pete Popov <ppopov@mvista.com> |
|---|---|
| Subject: | Re: R4600 V1.7 errata |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Wed, 4 Feb 2004 21:04:23 +0100 |
| Cc: | Linux/MIPS Development <linux-mips@linux-mips.org> |
| In-reply-to: | <1075910389.1170.42.camel@localhost.localdomain> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20040129102215.GC17760@ballina> <4018E322.9030801@gentoo.org> <20040131030435.GA24228@linux-mips.org> <20040131141027.GA11048@ballina> <20040201045258.GA4601@linux-mips.org> <20040203113928.GA28340@linux-mips.org> <20040203114252.GA27810@icm.edu.pl> <20040204154801.GB704@icm.edu.pl> <1075910389.1170.42.camel@localhost.localdomain> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Wed, Feb 04, 2004 at 07:59:49AM -0800, Pete Popov wrote: > > [...] > > > I assume it's safe to test it now? I'll build it for my R4600 V2.0 and > > > report in a while. Stay tuned. > > > > Works now. Thanks, guys. > > The latest cache updates break the Au1x kernel. I don't know yet exactly > what the problem is, but I tested with a snapshot before and after the > updates. The cache updates should specifically only affects systems that explicitly enable the cache workaround in <asm/war.h>; for any other the compiler should totally eleminate the workaround from the binary. Therefore my first guess would be pg-r4k.c. Ralf |
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