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Re: CVS Update@-mips.org: linux

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: CVS Update@-mips.org: linux
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Tue, 3 Feb 2004 16:30:33 +0100 (CET)
Cc: linux-mips@linux-mips.org
In-reply-to: <20040202152307.GB28673@linux-mips.org>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20040202141939Z8225226-9616+1555@linux-mips.org> <Pine.LNX.4.55.0402021611490.6182@jurand.ds.pg.gda.pl> <20040202152307.GB28673@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Mon, 2 Feb 2004, Ralf Baechle wrote:

> >  How do we assure tails of interrupt handlers don't trigger the errata?
> 
> The problem can only be triggered if instructions surrounding the
> cacheop use the dcache; exceptions such as interrupts are not relevant.

 Why?  How is an "eret" with its preceding instructions different to other 
instructions?  There may be a data cache miss soon before an "eret" and 
the response buffer may contain data.  And you may get an exeption right 
before a CACHE instruction.

> Which I'm really happy about.  Disabling interrupts is a problem in cases
> were we can't avoid page faults.

 I worry this is unsafe and given the unlikeliness of getting an interrupt
just between the dummy load and the CACHE instruction, this change creates
a completely obscure bug that'll bite unpredictably and possibly
invisibly, just corrupting data, every once and then.  But the situation
may be not that bad -- what does exactly happen when the erratum gets 
triggered?  Missing a Create_Dirty_Excl_D operation should itself be a 
performance hit only, but given the problems reported I suppose data gets 
corrupted, either in the cache or in the main memory.  Am I right?

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

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