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Re: R4600 V1.7 errata

To: linux-mips@linux-mips.org
Subject: Re: R4600 V1.7 errata
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 3 Feb 2004 12:52:36 +0100
In-reply-to: <20040203114252.GA27810@icm.edu.pl>
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References: <20040129102215.GC17760@ballina> <4018E322.9030801@gentoo.org> <20040131030435.GA24228@linux-mips.org> <20040131141027.GA11048@ballina> <20040201045258.GA4601@linux-mips.org> <20040203113928.GA28340@linux-mips.org> <20040203114252.GA27810@icm.edu.pl>
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On Tue, Feb 03, 2004 at 12:42:53PM +0100, Dominik 'Rathann' Mierzejewski wrote:

> On Tue, Feb 03, 2004 at 12:39:28PM +0100, Ralf Baechle wrote:
> [...] 
> > Jorik was so friendly to track down the patch in CVS that broke the R4600
> > V1.7 back in time.  With that as a start it was fairly easy to isolate the
> > problem further.  Seems we became victim of some erratum that affects the
> > operation of indexed I-cache flushes only.  Last night I commited a patch
> > that provides an optimized solution for the problem.
> 
> I assume it's safe to test it now? I'll build it for my R4600 V2.0 and
> report in a while. Stay tuned.

2.0 requires different workarounds which are already in place and functional
since quite some time.  We still lacking a fix for one important erratum of
the 2.0 but it seems pretty stable without.

Chip revs later than 2.0 do identify as 2.0 so if you're lucky your processor
is actually a post-2.0 and working just fine ...

  Ralf

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