| To: | karthikeyan natarajan <karthik_96cse@yahoo.com> |
|---|---|
| Subject: | Re: Doubt in timer interrupt |
| From: | Dominic Sweetman <dom@mips.com> |
| Date: | Fri, 23 Jan 2004 08:18:54 +0000 |
| Cc: | Dominic Sweetman <dom@mips.com>, linux-mips@linux-mips.org |
| In-reply-to: | <20040122092738.52844.qmail@web10105.mail.yahoo.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <16399.36167.575161.386963@doms-laptop.algor.co.uk> <20040122092738.52844.qmail@web10105.mail.yahoo.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
Karthi, > May i know the purpose of the NMI interrupt and > in what way it differ from the timer interrupt. On MIPS CPUs the NMI is a sort of second-class reset. You could use it for debugging and the kind of last-ditch everything-is-dead watchdog interrupt you might use in a high-availability system. Most systems don't connect it to anything. It's not for use for regular device interrupts at all. -- Dominic |
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