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Re: Doubt in timer interrupt

To: karthikeyan natarajan <karthik_96cse@yahoo.com>
Subject: Re: Doubt in timer interrupt
From: Dominic Sweetman <dom@mips.com>
Date: Thu, 22 Jan 2004 08:43:51 +0000
Cc: linux-mips@linux-mips.org
In-reply-to: <20040122072407.11156.qmail@web10102.mail.yahoo.com>
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References: <20040122072407.11156.qmail@web10102.mail.yahoo.com>
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Karthi,

>   In R4000 & descendent processors, interrupt number 7
> is being used for internal timer interrupt. From this
> i understand that the timer interrupt is also maskable
> when the IE bit in status register is cleared. If 
> somebody mask this interrupt for a long time 
> erroneously, then won't there be a problem in 
> maintaining the system time?

Yes, there may be a long delay.  So the standard way of using the
onchip counter to generate a periodic interrupt is that the counter
itself is allowed to free-run, keeping accurate time.

The 'Compare' register is then incremented by a fixed amount.

So long as the interrupt is not delayed by a whole tick, this keeps
perfect time.

I'm sure this is described in "See MIPS Run" - do you have a copy?

--
Dominic Sweetman
MIPS Technologies Inc



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