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Doubt in timer interrupt

To: linux-mips@linux-mips.org
Subject: Doubt in timer interrupt
From: karthikeyan natarajan <karthik_96cse@yahoo.com>
Date: Thu, 22 Jan 2004 07:24:07 +0000 (GMT)
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi All,

  In R4000 & descendent processors, interrupt number 7
is being used for internal timer interrupt. From this
i understand that the timer interrupt is also maskable
when the IE bit in status register is cleared. If 
somebody mask this interrupt for a long time 
erroneously, then won't there be a problem in 
maintaining the system time?
    Please correct me if i am wrong..

Does the system time is maintained via NMI?
   
Thanks in advance,
-karthi

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