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Re: In r4k, where does PC point to?

To: Dominic Sweetman <dom@mips.com>, Ralf Baechle <ralf@linux-mips.org>
Subject: Re: In r4k, where does PC point to?
From: karthikeyan natarajan <karthik_96cse@yahoo.com>
Date: Mon, 19 Jan 2004 15:14:03 +0000 (GMT)
Cc: linux-mips@linux-mips.org
In-reply-to: <16395.61512.498041.811385@gladsmuir.mips.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi Dominic Sweetman,

> > >     Basically, the PC points to the next
> instruction
> > > to
> > > be executed. But, in R4k, there are 8
> instructions
> > > getting executed in parallel. Where does the PC
> point
> > > to? My understanding is that PC points to the
> next 
> > > instruction that will be entered into the
> pipeline.
> > >     Please correct me if i am wrong..
> 
> Ralf Baechle (ralf@linux-mips.org) writes:
>  
> > The fact that instructions are issued in a
> pipeline is not visible in
> > the EPC value.
> 
> Which is true, but perhaps a bit cryptic given the
> question.
> 
> A MIPS CPU does not have a register called "PC".  In

In the r4k user manual, it is mentioned that there is
a special register PC in the core CPU (other than the 
HI & LO special registers). Could you please let me 
know the purpose of this register?

Thanks,
-karthi

> the MIPS
> architecture, "PC" is just slang meaning "the
> address of this
> instruction" - and only makes any sense if you're
> prepared to say
> WHICH instruction you mean.
> 
> There IS a register called "EPC" (for "exception
> PC").  When you
> take any kind of exception, it's the address of the
> first instruction
> which didn't get run because the CPU took the
> exception instead.  So
> EPC tells you where to jump back to after the
> exception handler runs.
> 
> Did any of that make any sense?
> 
> --
> Dominic Sweetman
> MIPS Technologies.
> 
> 
> 
>  

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