| To: | karthikeyan natarajan <karthik_96cse@yahoo.com> |
|---|---|
| Subject: | Re: How to configure the cache size in r4000 |
| From: | "Maciej W. Rozycki" <macro@ds2.pg.gda.pl> |
| Date: | Mon, 12 Jan 2004 13:51:55 +0100 (CET) |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20040111124828.71884.qmail@web10103.mail.yahoo.com> |
| Organization: | Technical University of Gdansk |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20040111124828.71884.qmail@web10103.mail.yahoo.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
On Sun, 11 Jan 2004, [iso-8859-1] karthikeyan natarajan wrote: > The cache size is modified by setting the IC/DC > bits in the 'config' register. Seems they are set only > by the hardware during the processor reset. And also, > those bits are mentioned as read only bits.. You cannot modify the size of the primary caches -- the values are hardwired to the amount of cache available in the processor (8kB+8kB for the original R4000). However, if you take appropriate precautions, you can alter the line sizes of the caches by modifying appropriate bits of cp0.config. -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | ptrace induced instruction cache bug?, Nathan Field |
|---|---|
| Next by Date: | Patch for MyCable XXS1500 for 2.4.24-pre1, Goswin von Brederlow |
| Previous by Thread: | Re: How to configure the cache size in r4000, Ralf Baechle |
| Next by Thread: | Re: How to configure the cache size in r4000, Ralf Baechle |
| Indexes: | [Date] [Thread] [Top] [All Lists] |