| To: | karthikeyan natarajan <karthik_96cse@yahoo.com> |
|---|---|
| Subject: | Re: How to configure the cache size in r4000 |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Mon, 12 Jan 2004 17:57:24 +0100 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20040111124828.71884.qmail@web10103.mail.yahoo.com> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20040111124828.71884.qmail@web10103.mail.yahoo.com> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4i |
On Sun, Jan 11, 2004 at 12:48:28PM +0000, karthikeyan natarajan wrote: > The cache size is modified by setting the IC/DC > bits in the 'config' register. Seems they are set only > by the hardware during the processor reset. And also, > those bits are mentioned as read only bits.. > Could you please let me know how can we instruct > the hardware to do so. Can we do this via s/w?. You can't. These bits are hardwired to indicate the cache size which is 8k per primary cache on the R4000. Ralf |
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