linux-mips
[Top] [All Lists]

Re: [patch] 2.4: Support for newer gcc/gas options

To: macro@ds2.pg.gda.pl
Subject: Re: [patch] 2.4: Support for newer gcc/gas options
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Tue, 23 Dec 2003 22:02:13 +0900 (JST)
Cc: ralf@linux-mips.org, linux-mips@linux-mips.org
In-reply-to: <Pine.LNX.4.55.0312161822240.8262@jurand.ds.pg.gda.pl>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <Pine.LNX.4.55.0312161822240.8262@jurand.ds.pg.gda.pl>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Tue, 16 Dec 2003 22:33:41 +0100 (CET), "Maciej W. Rozycki" 
>>>>> <macro@ds2.pg.gda.pl> said:
macro>  The patch implements a make macro called set_gccflags which
macro> accepts two sets of options consisting of a CPU name and an ISA
macro> name each.  Within both sets "-march=" and failing that
macro> "-mcpu=" is checked with the CPU name and the ISA name is
macro> checked simultaneously.  For gcc if the first set of options
macro> fails, the second one is selected even if it would lead to a
macro> failure.  For gas both sets are checked and if none succeeds,
macro> an empty set is selected.

With this patch, most r4k use MIPS3 ISA, right?

If so, please fix include/asm-mips/asm.h or arch/mips/kernel/entry.S
on 2.4 branch also.

As I wrote in August, handle_adel_int will be broken with MIPS3 ISA.
<http://www.linux-mips.org/archives/linux-mips/2003-08/msg00072.html>


Excerpt from include/asm-mips/asm.h:

#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS32)
#define REG_S           sw 
#define REG_L           lw 
#define REG_SUBU        subu
#define REG_ADDU        addu
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define REG_S           sd
#define REG_L           ld
#define REG_SUBU        dsubu
#define REG_ADDU        daddu
#endif

#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS32)
#define MFC0            mfc0
#define MTC0            mtc0
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MFC0            dmfc0
#define MTC0            dmtc0
#endif

Excerpt from arch/mips/kernel/entry.S:

#define __BUILD_clear_ade(exception)                                    \
                .set    reorder;                                        \
                MFC0    t0,CP0_BADVADDR;                                \
                .set    noreorder;                                      \
                REG_S   t0,PT_BVADDR(sp);                               \
                KMODE

With MIPS3 ISA, handle_adel_int will be:

8002630c <handle_adel_int> 40284000     dmfc0   t0,$8
80026310 <handle_adel_int+0x4> 00000000         nop
80026314 <handle_adel_int+0x8> ffa800a4         sd      t0,164(sp)

which is wrong for 32bit kernel.

---
Atsushi Nemoto

<Prev in Thread] Current Thread [Next in Thread>