Have got a one more doubt...
MIPS stands for Microprocessor without Interlocked
But, in the "R4400_Uman_book_Ed2.pdf" doc, it is
mentioned that the CPU general registers are
interlocked. I am bit confused after reading this doc.
Would be great if you clarify this doubt too...
> The MIPS architecture specifies a single delay slot
> after a branch
> or jump. The fact that the R4000 implementation
> (and pretty much
> any of the ones following) had a pipeline in which
> more instructions
> had already entered the pipe before the branch is
> resolved is not
> relevant to the architecture specification. In the
> case you
> mention, a single instruction is executed after the
> branch, as
> architecturally required, and any subsequent
> instructions in the
> pipe are killed.
> On Thu, 2003-12-18 at 22:01, karthikeyan natarajan
> > Hi All,
> > If this is not a right forum to ask this
> > please redirect me to the appropriate one...
> > Since R4000 is using the 8 stage pipeline,
> > instructions are already entered into the pipeline
> > when the branch instruction is executed. Out of
> > three instructions, the first instruction will be
> > executed for sure.
> > My question is:
> > What happens to the other two instruction that
> > in the delay slots? are they nullified?
> > Could anyone please shed some light on this.
> > Thanks much,
> > -karthi
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