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Re: Regarding branch delay instructions in R4000

To: karthikeyan natarajan <>
Subject: Re: Regarding branch delay instructions in R4000
From: Michael Uhler <>
Date: 18 Dec 2003 22:41:32 -0800
In-reply-to: <>
Original-recipient: rfc822;
References: <>
The MIPS architecture specifies a single delay slot after a branch
or jump.  The fact that the R4000 implementation (and pretty much
any of the ones following) had a pipeline in which more instructions
had already entered the pipe before the branch is resolved is not
relevant to the architecture specification.  In the case you
mention, a single instruction is executed after the branch, as
architecturally required, and any subsequent instructions in the
pipe are killed.


On Thu, 2003-12-18 at 22:01, karthikeyan natarajan wrote:
> Hi All,
>     If this is not a right forum to ask this Question,
> please redirect me to the appropriate one...
>     Since R4000 is using the 8 stage pipeline, three
> instructions are already entered into the pipeline
> when the branch instruction is executed. Out of these
> three instructions, the first instruction will be 
> executed for sure.
> My question is:
>     What happens to the other two instruction that are
> in the delay slots? are they nullified?
>     Could anyone please shed some light on this.
> Thanks much,
> -karthi
> =====
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