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Re: MIPS Interrupts.

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: MIPS Interrupts.
From: Jun Sun <jsun@mvista.com>
Date: Tue, 25 Nov 2003 16:31:04 -0800
Cc: "Kapoor, Pankaj" <pkapoor@telogy.com>, linux-mips@linux-mips.org, jsun@mvista.com
In-reply-to: <20031125230946.GA12422@linux-mips.org>; from ralf@linux-mips.org on Wed, Nov 26, 2003 at 12:09:46AM +0100
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <37A3C2F21006D611995100B0D0F9B73C02C8FCAE@tnint11.telogy.design.ti.com> <20031125230946.GA12422@linux-mips.org>
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On Wed, Nov 26, 2003 at 12:09:46AM +0100, Ralf Baechle wrote:
> On Tue, Nov 25, 2003 at 04:52:20PM -0500, Kapoor, Pankaj wrote:
> 
> > Now there are 2 cases that can happen 
> > 
> > 1. Since we have not exited the ISR and the exception level has still not 
> >    been restored there can be no more interrupts that are generated in the 
> >    system. In such a case does that mean that the all bottom half handlers 
> >    pending execution will run with interrupts disabled. 
> >    NOTE: This does not seem likely because the local_irq_enable routine
> >    calls _sti which clears the exception level in the status register and
> >    also sets the IE bit. 
> > 
> > 2. If we have large number of tasklets or if the bottom half handlers take
> >    time to execute, then we could get another timer interrupt or other
> >    device interrupts causing context saves which would cause the stack to
> >    grow and CRASH the system. 
> 
> Interrupts are disabled while the respective interrupt handler is running.
>

They are re-enabled for "bottom halves", i.e., in do_softirq().  I think
that is what the sender is worrying about.

Jun

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