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Re: MIPS addressing limits, Was: Re: CVS Update@-mips.org: linux

To: Jun Sun <jsun@mvista.com>
Subject: Re: MIPS addressing limits, Was: Re: CVS Update@-mips.org: linux
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 15 Oct 2003 19:42:16 +0200
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, linux-mips@linux-mips.org
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On Wed, Oct 15, 2003 at 10:19:02AM -0700, Jun Sun wrote:

> Isn't ia64 still using 3-level page tables?  Any performance data we
> can infer from theirs?

Very different MMU, IA64 data is hardly an indicator.  And anyway, the
result should be MIPS TLB refill handlers suck big chunky rocks through
a straw so should be rewritten ;-)

> I feel a little uneasy about ditching 3-level pagetable altogether.
> Leaving all the parameters configurable, including the possiblity of
> nullifying the second level and changing page size, seems to be a more 
> comforting thought.

3 levels are only needed if you can seriously say you're need more than
64GB of vmalloc space or processes larger than 64GB.  Little need for
that in the current universe though I know one institution which broke
the 1TB process size limit > 5 years ago.

  Ralf

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