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"sel" field in MTC0 instruction?

To: "'linux-mips@linux-mips.org'" <linux-mips@linux-mips.org>
Subject: "sel" field in MTC0 instruction?
From: "Babbellapati Syam Krishna (IFIN DC COM)" <Syam-Krishna.Babbellapati@infineon.com>
Date: Tue, 14 Oct 2003 11:16:20 +0530
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi there,
 
I am running linux on a MIPS64 5kc processor. From the Data Sheet and Software User's manual, I could see that we can access the various MIPS Performance Counters (Coprocessor 0, Register 25) by using the "sel" field of the MTC0 or MFC0 registers.
 

Format:   MTC0 rt, rd

        (OR) MTC0 rt, rd, sel

Based on the second format, I have written a new assembly languauge routine:

 
#define write_32bit_cp0_performance_register(register,value) \
__asm__ __volatile__( \
"mtc0\t%0,"STR(register)",sel\n\t" \
"nop" \
: : "r" (value));
 
"sel" in the above assembly instruction is a value of either 0, 1, 2 or 3 based on the register which we would like to write.
"sel" in the above code is newly introduced by us and if there is no sel then the code compiles properly but I guess we would always be accessing one register only in that case.
(A similar routine is written using "mfc0" also for reading the values back.)
 
But this code results in a compilation error:
{standard input}: Assembler messages:
{standard input}:41: Error: illegal operands `mtc0 $3,$25,0'
{standard input}:45: Error: illegal operands `mfc0 $5,$25,1'
where $25 is CP0_PERFORMANCE register.
 
The command used for compilation is:
mipsel-linux-gcc -c -I /home/syam/linux-2.4.20with095LTT/include/ -Wall -O2 -fomit-frame-pointer -fno-common -finline-limit=5000 -G 0 -mno-abicalls -fno-pic -mcpu=r4600 -mips2 -pipe -DMODULE -mlong-calls tempCache.c
 
 
Could someone help me in making me understand what is wrong here? Is it a problem with the syntax of the arguments or is there an assembler support which I am lacking for such an instruction?
 
Any kind of pointers would be of help.
 
Thank you,
Syam

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