| To: | exister99@velocitus.net |
|---|---|
| Subject: | Re: mips 32 bit HIGHMEM support |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Fri, 10 Oct 2003 16:59:49 +0200 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <20031009140319.GA17647@linux-mips.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <5334.156.153.254.2.1065650433.squirrel@webmail.rmci.net> <20031009140319.GA17647@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Thu, Oct 09, 2003 at 04:03:20PM +0200, Ralf Baechle wrote: > It's got a limitation - it only works on physically indexed D-caches or > more exactly processors that don't suffer from cache aliases. On > processors that have such aliases the necessary flushes are rather bad > for performance so this currently simply isn't suported. Small update - I changed the memory managment code to ignore highmem on cache configuration that are not supported by the highmem code. Ralf |
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