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Re: C0 config reg for 5k core

To: Mike Uhler <uhler@mips.com>
Subject: Re: C0 config reg for 5k core
From: David Kesselring <dkesselr@mmc.atmel.com>
Date: Mon, 11 Aug 2003 15:57:59 -0400 (EDT)
Cc: linux-mips@linux-mips.org
In-reply-to: <1060630328.1071.20.camel@uhler-linux.mips.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Is this reg, supposed to be the same among all processor or does it
differ?

On 11 Aug 2003, Mike Uhler wrote:

> Bit 0 of Config1 is FPU-present.  Bit 4 is "Performance counters
> present".  I guarantee you that the 5K family implements this
> pattern.
>
> /gmu
>
>
> On Mon, 2003-08-11 at 11:28, David Kesselring wrote:
> > Has anyone else built linux 2.4 for a 5k or 5kf core? When comparing cpu.h
> > and the MIPS64 5K Processor Core Family Software Users Manual it doesn't
> > look to me that the c0-config1 reg is defined the same way. Am I reading
> > something wrong? For example in the spec FPU flag is bit0 while in cpu.h
> > it is bit4. Seems pretty basic.
> >
> > David Kesselring
> > Atmel MMC
> > dkesselr@mmc.atmel.com
> > 919-462-6587
> --
>
> Michael Uhler, Chief Technology Officer
> MIPS Technologies, Inc.  Email: uhler@mips.com  Pager:uhler_p@mips.com
> 1225 Charleston Road     Voice:  (650)567-5025  FAX:   (650)567-5225
> Mountain View, CA 94043  Mobile: (650)868-6870  Admin: (650)567-5085
>
>
>
>

David Kesselring
Atmel MMC
dkesselr@mmc.atmel.com
919-462-6587


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