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Re: C0 config reg for 5k core

To: David Kesselring <dkesselr@mmc.atmel.com>
Subject: Re: C0 config reg for 5k core
From: Mike Uhler <uhler@mips.com>
Date: 11 Aug 2003 12:32:08 -0700
Cc: linux-mips@linux-mips.org
In-reply-to: <Pine.GSO.4.44.0308111422220.4449-100000@ares.mmc.atmel.com>
Organization: MIPS Technologies, Inc.
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <Pine.GSO.4.44.0308111422220.4449-100000@ares.mmc.atmel.com>
Sender: linux-mips-bounce@linux-mips.org
Bit 0 of Config1 is FPU-present.  Bit 4 is "Performance counters
present".  I guarantee you that the 5K family implements this
pattern.

/gmu


On Mon, 2003-08-11 at 11:28, David Kesselring wrote:
> Has anyone else built linux 2.4 for a 5k or 5kf core? When comparing cpu.h
> and the MIPS64 5K Processor Core Family Software Users Manual it doesn't
> look to me that the c0-config1 reg is defined the same way. Am I reading
> something wrong? For example in the spec FPU flag is bit0 while in cpu.h
> it is bit4. Seems pretty basic.
> 
> David Kesselring
> Atmel MMC
> dkesselr@mmc.atmel.com
> 919-462-6587
-- 

Michael Uhler, Chief Technology Officer
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