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Re: RM7k cache_flush_sigtramp

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: RM7k cache_flush_sigtramp
From: Fuxin Zhang <fxzhang@ict.ac.cn>
Date: Thu, 31 Jul 2003 20:57:59 +0800
Cc: MAKE FUN PRANK CALLS <linux-mips@linux-mips.org>
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Ralf Baechle wrote:

On Thu, Jul 31, 2003 at 09:56:08AM +0800, Fuxin Zhang wrote:
Date:   Thu, 31 Jul 2003 09:56:08 +0800
From:   Fuxin Zhang <fxzhang@ict.ac.cn>
To:     MAKE FUN PRANK CALLS <linux-mips@linux-mips.org>
       ^^^^^^^^^^^^^^^^^^^^

Funny name for the list :-)

r4k_cache_flush_sigtrap seems not enough for RM7000 cpus because
there is a writebuffer between L1 dcache & L2 cache,so the written back
block may not be seen by icache. This small patch fixes crashes of my
Xserver on ev64240.

It would seem a similar fix is also needed in other places then?

I have not thought about it further. But
1. I implement wb_flush for this board,using sync and uncached read. Just in case
     so many buffer on the cpu and system bridge will surprise me.
2. There are still occasionally oops, especially with IO activities,e.g.,when fscking a disk.

What would should suggest to look at? Some flushes will go through all levels of cache,
I think they should be safe. Will check later.

Thanks.


 Ralf





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