| To: | Fuxin Zhang <fxzhang@ict.ac.cn> |
|---|---|
| Subject: | Re: RM7k cache_flush_sigtramp |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Thu, 31 Jul 2003 13:46:39 +0200 |
| Cc: | MAKE FUN PRANK CALLS <linux-mips@linux-mips.org> |
| In-reply-to: | <3F287738.1040203@ict.ac.cn> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <3F287738.1040203@ict.ac.cn> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Thu, Jul 31, 2003 at 09:56:08AM +0800, Fuxin Zhang wrote:
> Date: Thu, 31 Jul 2003 09:56:08 +0800
> From: Fuxin Zhang <fxzhang@ict.ac.cn>
> To: MAKE FUN PRANK CALLS <linux-mips@linux-mips.org>
^^^^^^^^^^^^^^^^^^^^
Funny name for the list :-)
> r4k_cache_flush_sigtrap seems not enough for RM7000 cpus because
> there is a writebuffer between L1 dcache & L2 cache,so the written back
> block may not be seen by icache. This small patch fixes crashes of my
> Xserver on ev64240.
It would seem a similar fix is also needed in other places then?
Ralf
|
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: mmap'ed memory cacheable or uncheable, Ralf Baechle |
|---|---|
| Next by Date: | Re: RM7k cache_flush_sigtramp, Fuxin Zhang |
| Previous by Thread: | RM7k cache_flush_sigtramp, Fuxin Zhang |
| Next by Thread: | Re: RM7k cache_flush_sigtramp, Fuxin Zhang |
| Indexes: | [Date] [Thread] [Top] [All Lists] |