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Re: cache code fix for c-tx39.c

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: cache code fix for c-tx39.c
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Wed, 16 Jul 2003 19:58:13 +0900 (JST)
In-reply-to: <20030716.195514.71083728.nemoto@toshiba-tops.co.jp>
Organization: TOSHIBA Personal Computer System Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030709124821Z8225210-1272+3285@linux-mips.org> <20030716.195514.71083728.nemoto@toshiba-tops.co.jp>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Wed, 16 Jul 2003 19:55:14 +0900 (JST), Atsushi Nemoto 
>>>>> <anemo@mba.ocn.ne.jp> said:
>> Log message: Cache code fixes.

anemo> Please fix c-tx39.c also.  This is a patch for 2.4 branch.

And this is one for trunk (2.6).

diff -ur linux-mips-cvs-2.6/arch/mips/mm/c-tx39.c 
linux.new-2.6/arch/mips/mm/c-tx39.c
--- linux-mips-cvs-2.6/arch/mips/mm/c-tx39.c    Wed Jul 16 19:49:27 2003
+++ linux.new-2.6/arch/mips/mm/c-tx39.c Wed Jul 16 19:52:42 2003
@@ -25,9 +25,6 @@
 
 /* For R3000 cores with R4000 style caches */
 static unsigned long icache_size, dcache_size;         /* Size in bytes */
-static unsigned long icache_way_size, dcache_way_size; /* Size divided by ways 
*/
-#define scache_size 0
-#define scache_way_size 0
 
 #include <asm/r4kcache.h>
 
@@ -474,15 +471,15 @@
                break;
        }
 
-       icache_way_size = icache_size / current_cpu_data.icache.ways;
-       dcache_way_size = dcache_size / current_cpu_data.dcache.ways;
+       current_cpu_data.icache.waysize = icache_size / 
current_cpu_data.icache.ways;
+       current_cpu_data.dcache.waysize = dcache_size / 
current_cpu_data.dcache.ways;
 
        current_cpu_data.icache.sets =
-               icache_way_size / current_cpu_data.icache.linesz;
+               current_cpu_data.icache.waysize / 
current_cpu_data.icache.linesz;
        current_cpu_data.dcache.sets =
-               dcache_way_size / current_cpu_data.dcache.linesz;
+               current_cpu_data.dcache.waysize / 
current_cpu_data.dcache.linesz;
 
-       if (dcache_way_size > PAGE_SIZE)
+       if (current_cpu_data.dcache.waysize > PAGE_SIZE)
                current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
 
        current_cpu_data.icache.waybit = 0;
---
Atsushi Nemoto

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