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cache code fix for c-tx39.c (Re: CVS Update@-mips.org: linux)

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: cache code fix for c-tx39.c (Re: CVS Update@-mips.org: linux)
From: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Date: Wed, 16 Jul 2003 19:55:14 +0900 (JST)
In-reply-to: <20030709124821Z8225210-1272+3285@linux-mips.org>
Organization: TOSHIBA Personal Computer System Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030709124821Z8225210-1272+3285@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Wed,  9 Jul 2003 13:48:16 +0100, ralf@linux-mips.org said:
> Changes by:   ralf@ftp.linux-mips.org 03/07/09 13:48:16
> 
> Modified files:
>       arch/mips/mm   : Tag: linux_2_4 c-r4k.c 
>       arch/mips64/mm : Tag: linux_2_4 c-r4k.c 
>       include/asm-mips: Tag: linux_2_4 processor.h r4kcache.h 
>       include/asm-mips64: Tag: linux_2_4 processor.h 
> 
> Log message:
>       Cache code fixes.

Please fix c-tx39.c also.  This is a patch for 2.4 branch.

diff -ur linux-mips-cvs/arch/mips/mm/c-tx39.c linux.new/arch/mips/mm/c-tx39.c
--- linux-mips-cvs/arch/mips/mm/c-tx39.c        Tue May  6 09:40:58 2003
+++ linux.new/arch/mips/mm/c-tx39.c     Wed Jul 16 19:39:55 2003
@@ -25,9 +25,6 @@
 
 /* For R3000 cores with R4000 style caches */
 static unsigned long icache_size, dcache_size;         /* Size in bytes */
-static unsigned long icache_way_size, dcache_way_size; /* Size divided by ways 
*/
-#define scache_size 0
-#define scache_way_size 0
 
 #include <asm/r4kcache.h>
 
@@ -473,15 +470,15 @@
                break;
        }
 
-       icache_way_size = icache_size / current_cpu_data.icache.ways;
-       dcache_way_size = dcache_size / current_cpu_data.dcache.ways;
+       current_cpu_data.icache.waysize = icache_size / 
current_cpu_data.icache.ways;
+       current_cpu_data.dcache.waysize = dcache_size / 
current_cpu_data.dcache.ways;
 
        current_cpu_data.icache.sets =
-               icache_way_size / current_cpu_data.icache.linesz;
+               current_cpu_data.icache.waysize / 
current_cpu_data.icache.linesz;
        current_cpu_data.dcache.sets =
-               dcache_way_size / current_cpu_data.dcache.linesz;
+               current_cpu_data.dcache.waysize / 
current_cpu_data.dcache.linesz;
 
-       if (dcache_way_size > PAGE_SIZE)
+       if (current_cpu_data.dcache.waysize > PAGE_SIZE)
                current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
 
        current_cpu_data.icache.waybit = 0;
---
Atsushi Nemoto

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