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Re: wired tlb entry?

To: Joseph Chiu <joseph@omnilux.net>
Subject: Re: wired tlb entry?
From: Pete Popov <ppopov@mvista.com>
Date: 17 Jun 2003 10:18:54 -0700
Cc: Linux MIPS mailing list <linux-mips@linux-mips.org>
In-reply-to: <BPEELMGAINDCONKDGDNCOEFBDMAA.joseph@omnilux.net>
Organization: MontaVista Software
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <BPEELMGAINDCONKDGDNCOEFBDMAA.joseph@omnilux.net>
Sender: linux-mips-bounce@linux-mips.org
On Mon, 2003-06-16 at 17:36, Joseph Chiu wrote:
> Hi,
> Is there a (proper) way to add a page entry in the TLB it's always valid?
> Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
> to oops under heavy interrupt loading.
> It seems to me that the page entry in the TLB is getting flushed out under
> the activity; and when the ioremap'd memory region is accesses, the
> exception handling for the missing translation does not run.
> 
> I'm afraid my two days of googling hasn't turned up the right information.
> I think I just don't know the right terminology and I hope someone can at
> least point me in the right direction.
> Thanks.
> Joseph
> (I am running 2.4.18-mips)

So is this a kernel from linux-mips.org?  Are you using the 36 bit I/O
patch in that kernel, or the pseudo-address translation hack that I
removed later? What pcmcia I/O card are you using and what tests are you
running?

Pete


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