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wired tlb entry?

To: "Linux-MIPS" <linux-mips@linux-mips.org>
Subject: wired tlb entry?
From: "Joseph Chiu" <joseph@omnilux.net>
Date: Mon, 16 Jun 2003 17:36:58 -0700
Importance: Normal
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
Hi,
Is there a (proper) way to add a page entry in the TLB it's always valid?
Specifically, accesses to memory-mapped hardware (PCMCIA) causes the kernel
to oops under heavy interrupt loading.
It seems to me that the page entry in the TLB is getting flushed out under
the activity; and when the ioremap'd memory region is accesses, the
exception handling for the missing translation does not run.

I'm afraid my two days of googling hasn't turned up the right information.
I think I just don't know the right terminology and I hope someone can at
least point me in the right direction.
Thanks.
Joseph
(I am running 2.4.18-mips)



--
Joseph Chiu, Senior Engineer, Omnilux, Inc.
joseph@omnilux.net  (626) 535-2819
The sun will come up tomorrow.  Bet your bottom dollar that tomorrow,
things'll be back.


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