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Re: CVS Update@-mips.org: linux

To: linux-mips@linux-mips.org, ralf@linux-mips.org
Subject: Re: CVS Update@-mips.org: linux
From: Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
Date: Mon, 16 Jun 2003 10:19:11 +0900 (JST)
In-reply-to: <20030615004718Z8225220-1272+2582@linux-mips.org>
Organization: TOSHIBA Personal Computer System Corporation
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030615004718Z8225220-1272+2582@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
>>>>> On Sun, 15 Jun 2003 01:47:13 +0100, ralf@linux-mips.org said:
> Modified files:
>       arch/mips64    : Tag: linux_2_4 Makefile 
>       include/asm-mips64: Tag: linux_2_4 processor.h r4kcache.h 

> Log message:
>       Support GT64120 boards with 64-bit kernels also.

This corrupts mips64/mm/c-r4k.c.  Please apply this patch also.


diff -u linux-mips-cvs/arch/mips64/mm/c-r4k.c linux.new/arch/mips64/mm/c-r4k.c
--- linux-mips-cvs/arch/mips64/mm/c-r4k.c       Mon Apr 28 09:44:53 2003
+++ linux.new/arch/mips64/mm/c-r4k.c    Mon Jun 16 09:59:38 2003
@@ -26,7 +26,6 @@
 
 /* Primary cache parameters. */
 static unsigned long icache_size, dcache_size, scache_size;
-unsigned long icache_way_size, dcache_way_size, scache_way_size;
 static unsigned long scache_size;
 
 #include <asm/cacheops.h>
@@ -848,8 +847,8 @@
                panic("Improper R4000SC processor configuration detected");
 
        /* compute a couple of other cache variables */
-       icache_way_size = icache_size / c->icache.ways;
-       dcache_way_size = dcache_size / c->dcache.ways;
+       c->icache.waysize = icache_size / c->icache.ways;
+       c->dcache.waysize = dcache_size / c->dcache.ways;
 
        c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
        c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
@@ -862,7 +861,7 @@
         */
        if (current_cpu_data.cputype != CPU_R10000 &&
            current_cpu_data.cputype != CPU_R12000)
-               if (dcache_way_size > PAGE_SIZE)
+               if (c->dcache.waysize > PAGE_SIZE)
                        c->dcache.flags |= MIPS_CACHE_ALIASES;
 
        if (config & 0x8)               /* VI bit */
diff -u linux-mips-cvs/arch/mips64/mm/sc-rm7k.c 
linux.new/arch/mips64/mm/sc-rm7k.c
--- linux-mips-cvs/arch/mips64/mm/sc-rm7k.c     Fri Apr 18 10:23:12 2003
+++ linux.new/arch/mips64/mm/sc-rm7k.c  Mon Jun 16 09:59:59 2003
@@ -20,8 +20,6 @@
 /* Secondary cache parameters. */
 #define scache_size    (256*1024)      /* Fixed to 256KiB on RM7000 */
 
-extern unsigned long icache_way_size, dcache_way_size;
-
 #include <asm/r4kcache.h>
 
 int rm7k_tcache_enabled;
---
Atsushi Nemoto

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