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Re: [RFC] synchronized CPU count registers on SMP machines

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [RFC] synchronized CPU count registers on SMP machines
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
Date: 05 Jun 2003 11:45:03 +0100
Cc: Jun Sun <jsun@mvista.com>, linux-mips@linux-mips.org
In-reply-to: <20030605001232.GA5626@linux-mips.org>
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Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030604153930.H19122@mvista.com> <20030604231547.GA22410@linux-mips.org> <20030604164652.J19122@mvista.com> <20030605001232.GA5626@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
On Iau, 2003-06-05 at 01:12, Ralf Baechle wrote:
> You loose.  The reasons why SGI did construct their systems that way are
> still valid.  It can be quite tricky to distribute the clock in large
> systems - even for a moderate definition of large.  And for ccNUMAs which
> are going to show up on the embedded market sooner or later it's easy
> for the lazy designer to use several clock sources anyway.  Note our
> current time code for will not work properly if clocks diverge on the
> slightest bit - among other things the standards mandate time to
> monotonically increase.

Actually the standards are suprisingly lax. I had the same assumptions
but people who went and read the spec in detail found Posix is a lot
more relaxed (except about CLOCK_MONOTONIC).

What seems to be happening in the PC and Sparc worlds is vendors are
running a seperate lower accuracy global clock source (eg the HPET on
AMD64)


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