| To: | "Krishnakumar. R" <krishnakumar@naturesoft.net> |
|---|---|
| Subject: | Re: Single stepping in mips |
| From: | Ralf Baechle <ralf@linux-mips.org> |
| Date: | Wed, 4 Jun 2003 07:18:18 +0200 |
| Cc: | linux-mips@linux-mips.org |
| In-reply-to: | <200306040918.01943.krishnakumar@naturesoft.net> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <200306040918.01943.krishnakumar@naturesoft.net> |
| Sender: | linux-mips-bounce@linux-mips.org |
| User-agent: | Mutt/1.4.1i |
On Wed, Jun 04, 2003 at 09:18:01AM +0530, Krishnakumar. R wrote: > How can we single step through an instruction > in mips architecture. > > In intel 386 architecture if we set TF flag > of the EFLAGS register a trap will be generated > after every instruction. Is there a way in > mips to do the same. On most MIPS processors there is no singlestepping feature. You have to manual insert a breakpoint into the instruction stream and deal with the exception. Ralf |
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