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TLB mapping questions

To: linux-mips@linux-mips.org
Subject: TLB mapping questions
From: "Erik J. Green" <erik@greendragon.org>
Date: Sat, 19 Apr 2003 05:32:50 +0000
Original-recipient: rfc822;linux-mips@linux-mips.org
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Hello again, I have more newbie questions for you all.


I *think* I understand how the TLB translates addresses for ckseg2 in mips64. 
Can someone tell me if my understanding is correct?  

Given: Physical memory starts at 0x0000000020004000;

Therefore, an offset 0x2000 from the start of physical memory should be at 

0x0000000020006000, or 0xa000000020006000 as a 64 bit xkphys address.

So if I construct a TLB entry such that cp0_entryhi is 0xffffffffc0002000, and
cp0_entrylo0 has a PFN address of 0x0000000020006, giving it the correct ASID
(0) and valid bitflags(VG), I should be able to access the physical memory
offset above using the ckseg2 virtual address 0xffffffffc0002000?  

Again, if I understand this, the physical address to be referenced will be
constructed from the low order 12 bits of the ckseg2 address (in this case 000)
and the pfn address stored in the TLB entry giving 0x0000000020006000, which is
the physical RAM address.  This is provided that I've constructed the TLB entry
correctly so that it's matched for the address reference given.

Of course, the reason I discuss all this is that the above doesn't work. =)  



Erik 


-- 
Erik J. Green
erik@greendragon.org

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