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Re: Basic cache questions

To: Steve Taylor <godzilla1357@yahoo.com>
Subject: Re: Basic cache questions
From: Jun Sun <jsun@mvista.com>
Date: Tue, 15 Apr 2003 16:40:27 -0700
Cc: linux-mips@linux-mips.org, jsun@mvista.com
In-reply-to: <20030415221914.47873.qmail@web14503.mail.yahoo.com>; from godzilla1357@yahoo.com on Tue, Apr 15, 2003 at 03:19:14PM -0700
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On Tue, Apr 15, 2003 at 03:19:14PM -0700, Steve Taylor wrote:
> Hello All,   I am hoping some of you mips-linux gurus will be able to help me 
> give me some tips and help me get started on some cache stuff which I want to 
> do. (I know decently well about caches - but only at a theoretical Hennessy & 
> Patterson level - and have just started looking under arch/mips/mm to 
> familiarize myself with the mips-linux implementation).   Here's what I want 
> to do - I have a CPU with 4 way SA I and D caches, and I want to write a 
> module that will lock a certain memory region in these caches (for example, 
> let's say I want to lock the ISR in the I-cache). So my questions are a) Is 
> the kernel going to crash if I try to mess around with the caches like 
> locking out a particular way of the cache or something like that? b) I'm sure 
> there are many issues and complications involved in this that I probably 
> havent even thought of  - any obvious and/or subtle pitfalls? and c) Do you 
> think locking out, say, an entire way of a 4-way cache for a dedicated 
> frequently used !
> !
> routine improves or degrades overall system performance?   TIA, -Steve.

If the cache locking can survive flushing, i.e., locked cache line
remained valid and locked even after cache invalidation ops, I guess
you are probably OK.

I have looked the performance issues with cache locking on a two-way
cache system.  There was not much performance gain.

Jun

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