| To: | ralf@linux-mips.org |
|---|---|
| Subject: | Re: End c-tx49.c's misserable existence |
| From: | Atsushi Nemoto <anemo@mba.ocn.ne.jp> |
| Date: | Wed, 16 Apr 2003 00:15:09 +0900 (JST) |
| Cc: | nemoto@toshiba-tops.co.jp, linux-mips@linux-mips.org |
| In-reply-to: | <20030414174825.A9808@linux-mips.org> |
| Original-recipient: | rfc822;linux-mips@linux-mips.org |
| References: | <20030414055038.A29923@linux-mips.org> <20030414.152903.41628304.nemoto@toshiba-tops.co.jp> <20030414174825.A9808@linux-mips.org> |
| Sender: | linux-mips-bounce@linux-mips.org |
>>>>> On Mon, 14 Apr 2003 17:48:25 +0200, Ralf Baechle <ralf@linux-mips.org> >>>>> said: >> One more request. Please enclose R4600_V1_HIT_CACHEOP_WAR and >> R4600_V2_HIT_CACHEOP_WAR with appropriate CONFIG_CPU_XXX. I do not >> know what CPUs need this workaround... (at least TX49 does not need >> this) ralf> I'll leave it unconditionally enabled for now because the ralf> Makefiles could behave in undefined ways if multiple ralf> CONFIG_CPU_* options are selected and quite a few systems ralf> support both the R4600 and other processors like the Indy. ralf> Another day. I have been misunderstood that people who needs the workaround always select CONFIG_CPU_R4X00. But it is not true. Now I understand. But recent reorganization increased a number of c-r4k.c users somewhat. How about introducing new config macros such as CONFIG_R4600_V1_WORKAROUNDS ? --- Atsushi Nemoto |
| <Prev in Thread] | Current Thread | [Next in Thread> |
|---|---|---|
| ||
| Previous by Date: | Re: [PATCH] waybit not set for MIPS32/MIPS64 caches, Ralf Baechle |
|---|---|
| Next by Date: | Re: End c-tx49.c's misserable existence, Ralf Baechle |
| Previous by Thread: | Re: End c-tx49.c's misserable existence, Ralf Baechle |
| Next by Thread: | Re: End c-tx49.c's misserable existence, Ralf Baechle |
| Indexes: | [Date] [Thread] [Top] [All Lists] |