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Re: End c-tx49.c's misserable existence

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: End c-tx49.c's misserable existence
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 14 Apr 2003 17:48:25 +0200
Cc: nemoto@toshiba-tops.co.jp, linux-mips@linux-mips.org
In-reply-to: <20030414.152903.41628304.nemoto@toshiba-tops.co.jp>; from anemo@mba.ocn.ne.jp on Mon, Apr 14, 2003 at 03:29:03PM +0900
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References: <20030412163215Z8225197-1272+1264@linux-mips.org> <20030414.123514.74756574.nemoto@toshiba-tops.co.jp> <20030414055038.A29923@linux-mips.org> <20030414.152903.41628304.nemoto@toshiba-tops.co.jp>
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On Mon, Apr 14, 2003 at 03:29:03PM +0900, Atsushi Nemoto wrote:

> >>>>> On Mon, 14 Apr 2003 05:50:38 +0200, Ralf Baechle <ralf@linux-mips.org> 
> >>>>> said:
> ralf> Excellent.  This should provide a good performance boost for the
> ralf> TX49 also as disabling the I-cache during the flush made the
> ralf> operation even slower than it has to be.
> 
> Thank you for quick response.
> 
> One more request.  Please enclose R4600_V1_HIT_CACHEOP_WAR and
> R4600_V2_HIT_CACHEOP_WAR with appropriate CONFIG_CPU_XXX.  I do not
> know what CPUs need this workaround... (at least TX49 does not need
> this)

I'll leave it unconditionally enabled for now because the Makefiles could
behave in undefined ways if multiple CONFIG_CPU_* options are selected
and quite a few systems support both the R4600 and other processors like
the Indy.  Another day.

  Ralf

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