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Re: End c-tx49.c's misserable existence

To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: End c-tx49.c's misserable existence
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 14 Apr 2003 05:50:38 +0200
Cc: linux-mips@linux-mips.org, Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
In-reply-to: <20030414.123514.74756574.nemoto@toshiba-tops.co.jp>; from anemo@mba.ocn.ne.jp on Mon, Apr 14, 2003 at 12:35:14PM +0900
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030412163215Z8225197-1272+1264@linux-mips.org> <20030414.123514.74756574.nemoto@toshiba-tops.co.jp>
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On Mon, Apr 14, 2003 at 12:35:14PM +0900, Atsushi Nemoto wrote:

> TOSHIBA_ICACHE_WAR can be removed.  This workaround is not needed
> if kernel does not modify the cache codes itself in run-time.
> 
> When I wrote c-tx49.c I blindly followed the statement in TX49/H2
> manual's statement. ("If the instruction (i.e. CACHE) is issued for
> the line which this instruction itself exists, the following operation
> is not guaranteed.")  Now I know this warning is only for
> self-modified code.  There must be no problem if the codes is not
> modified in run-time.  So please remove all TOSHIBA_ICACHE_WAR stuff
> and make c-r4k.c more clean.

Excellent.  This should provide a good performance boost for the TX49
also as disabling the I-cache during the flush made the operation even
slower than it has to be.

  Ralf

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