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Re: way selection bit for multi-way cache

To: Ralf Baechle <>
Subject: Re: way selection bit for multi-way cache
From: Dominic Sweetman <>
Date: Fri, 11 Apr 2003 07:33:04 +0100
Cc: Mike Uhler <>, Jun Sun <>,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <>
Mike wrote:

> > I'm not sure what you mean by TLB translations required for hit
> > cacheops.  If you mean the Index Writeback or Index Invalidate
> > functions, note that you can (and should) use a kseg0 address to
> > do this.

Mike was proposing a kseg0 address translating to the right physical
address, and used with a hit-type cacheop.  I believe Ralf (and Linux)
are just assuming that's no good because it doesn't work if you have
cacheable memory above 512Mbytes physical address.

I wonder whether anything really bad would happen if you temporarily
changed the (machine) ASID to that of the address space you wanted to


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