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Re: way selection bit for multi-way cache

To: Ralf Baechle <ralf@linux-mips.org>
Subject: Re: way selection bit for multi-way cache
From: Dominic Sweetman <dom@mips.com>
Date: Fri, 11 Apr 2003 07:33:04 +0100
Cc: Mike Uhler <uhler@mips.com>, Jun Sun <jsun@mvista.com>, linux-mips@linux-mips.org
In-reply-to: <20030410225212.A3294@linux-mips.org>
Original-recipient: rfc822;linux-mips@linux-mips.org
References: <20030410220906.B519@linux-mips.org> <200304102028.h3AKSf211575@uhler-linux.mips.com> <20030410225212.A3294@linux-mips.org>
Sender: linux-mips-bounce@linux-mips.org
Mike wrote:

> > I'm not sure what you mean by TLB translations required for hit
> > cacheops.  If you mean the Index Writeback or Index Invalidate
> > functions, note that you can (and should) use a kseg0 address to
> > do this.

Mike was proposing a kseg0 address translating to the right physical
address, and used with a hit-type cacheop.  I believe Ralf (and Linux)
are just assuming that's no good because it doesn't work if you have
cacheable memory above 512Mbytes physical address.

I wonder whether anything really bad would happen if you temporarily
changed the (machine) ASID to that of the address space you wanted to
invalidate?

--
Dominic


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