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Re: way selection bit for multi-way cache

To: Mike Uhler <uhler@mips.com>
Subject: Re: way selection bit for multi-way cache
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 10 Apr 2003 21:24:30 +0200
Cc: Jun Sun <jsun@mvista.com>, linux-mips@linux-mips.org
In-reply-to: <200304101850.h3AIorK11089@uhler-linux.mips.com>; from uhler@mips.com on Thu, Apr 10, 2003 at 11:50:53AM -0700
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On Thu, Apr 10, 2003 at 11:50:53AM -0700, Mike Uhler wrote:

> I can't comment on anything but MIPS32 and MIPS64 CPUs, but the
> MIPS32 and MIPS64 standard is to use the bits above the index field
> to specify the way.  See the figure entitled "Usage of Address Fields
> to Select Index and Way" in the CACHE instruction description of the
> MIPS32 and MIPS64 Architecture for Programmer's manuals.

The question came up between Jun and me when revising the way of handling
multi-way caches.  There is the MIPS32 / MIPS64 way of selecting the
cache way - but that scheme was originally already introduced by the
R4600.  The second somewhat less common scheme is using the lowest bits
of the address.  That was originally introduced with the R10000 but a
few other processors such as the R5432 and the TX49 series are using it
as well.  Unfortunately there has been way to much creativity (usually
a positive property but ...) among designers so this posting is an
attempt to achieve completeness.

  Ralf

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