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Re: way selection bit for multi-way cache

To: Mike Uhler <uhler@mips.com>
Subject: Re: way selection bit for multi-way cache
From: Jun Sun <jsun@mvista.com>
Date: Thu, 10 Apr 2003 11:55:52 -0700
Cc: linux-mips@linux-mips.org, jsun@mvista.com
In-reply-to: <200304101850.h3AIorK11089@uhler-linux.mips.com>; from uhler@mips.com on Thu, Apr 10, 2003 at 11:50:53AM -0700
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References: <20030410110527.E9002@mvista.com> <200304101850.h3AIorK11089@uhler-linux.mips.com>
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On Thu, Apr 10, 2003 at 11:50:53AM -0700, Mike Uhler wrote:
> > 
> > If a cache is multi-way set associative cache, one must
> > select the way for indexed cache operations.
> > 
> > The most common way selection is to use MSBs in the addressing
> > range of the whole cache size.  In other word, a two-way
> > cache of size d would use bit (log(d)-1) to select the way.
> > 
> > Some other CPUs often the LSB(s) in the address to select
> > ways.  Examples include R5432, R5500, TX49, TX39.  Does
> > anybody know other such CPUs?
> > 
> > And I think I have seen a third kind way selection, but I
> > can't remember which CPU it is.  Does anybody know any
> > other way selection schemes?
> > 
> > Thanks.
> > 
> > Jun
> > 
> 
> I can't comment on anything but MIPS32 and MIPS64 CPUs, but the
> MIPS32 and MIPS64 standard is to use the bits above the index field
> to specify the way.  

Yes.  This is same as the "most common case" as I said above.
Maybe this is a better way to phrase it.  :)

Jun

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