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Re: way selection bit for multi-way cache

To: Jun Sun <jsun@mvista.com>
Subject: Re: way selection bit for multi-way cache
From: "Mike Uhler" <uhler@mips.com>
Date: Thu, 10 Apr 2003 11:50:53 -0700
Cc: linux-mips@linux-mips.org
In-reply-to: Your message of "Thu, 10 Apr 2003 11:05:27 PDT." <20030410110527.E9002@mvista.com>
Original-recipient: rfc822;linux-mips@linux-mips.org
Reply-to: uhler@mips.com
Sender: linux-mips-bounce@linux-mips.org
> 
> If a cache is multi-way set associative cache, one must
> select the way for indexed cache operations.
> 
> The most common way selection is to use MSBs in the addressing
> range of the whole cache size.  In other word, a two-way
> cache of size d would use bit (log(d)-1) to select the way.
> 
> Some other CPUs often the LSB(s) in the address to select
> ways.  Examples include R5432, R5500, TX49, TX39.  Does
> anybody know other such CPUs?
> 
> And I think I have seen a third kind way selection, but I
> can't remember which CPU it is.  Does anybody know any
> other way selection schemes?
> 
> Thanks.
> 
> Jun
> 

I can't comment on anything but MIPS32 and MIPS64 CPUs, but the
MIPS32 and MIPS64 standard is to use the bits above the index field
to specify the way.  See the figure entitled "Usage of Address Fields
to Select Index and Way" in the CACHE instruction description of the
MIPS32 and MIPS64 Architecture for Programmer's manuals.

/gmu

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