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way selection bit for multi-way cache

To: linux-mips@linux-mips.org
Subject: way selection bit for multi-way cache
From: Jun Sun <jsun@mvista.com>
Date: Thu, 10 Apr 2003 11:05:27 -0700
Cc: jsun@mvista.com
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
User-agent: Mutt/1.2.5i
If a cache is multi-way set associative cache, one must
select the way for indexed cache operations.

The most common way selection is to use MSBs in the addressing
range of the whole cache size.  In other word, a two-way
cache of size d would use bit (log(d)-1) to select the way.

Some other CPUs often the LSB(s) in the address to select
ways.  Examples include R5432, R5500, TX49, TX39.  Does
anybody know other such CPUs?

And I think I have seen a third kind way selection, but I
can't remember which CPU it is.  Does anybody know any
other way selection schemes?

Thanks.

Jun

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