I'm working on getting mips-linux up and running on my Octane, which may be an
impossible task. I am new to the MIPS architecture, and I'm absorbing a lot of
information rapidly from MIPS Inc. manuals, See MIPS Run, et. al., but I have
been banging my head against the wall for a couple days trying to get a simple
First, my Octane works just fine with Irix 6.5.17. Configuration is a R12K
CPU/300 mhz, 256MB RAM, 1 18G disk, ethernet connection. I boot using bootp.
I've used the network to boot fx, a copy of the irix kernel, etc.
I get the following messages when I try to boot the (very slightly) modified
linux kernel I am working with:
Obtaining /vmlinux.64 from server
1813568+1150976+172144 entry: 0xa8000000211c4000
*** PROM write error on cacheline 0x1fcd3b00 at PC=0x211c4018
The PC address is the first instruction in head.S (mips64) that touches the
control register. I've tried multiple fixes, including initializing the whole
TLB before the error occurs. Same error.
Can anyone tell me:
1) What does this error text mean exactly?
2) What is "RA"? The address is a location in the PROM text/stack section.
3) Am I missing something simple? An initialization, a rule I'm not following?
objdump of the head.S I am using is below.
Thanks for any clues you can provide. I'm excited to get working on this
machine if I can just learn MIPS =\
Disassembly of section .text.init:
a8000000211c4000: 37bd000f ori sp,sp,0xf
a8000000211c4004: 3bbd000f xori sp,sp,0xf
a8000000211c4008: 3c0c211c lui t0,0x211c
a8000000211c400c: 258c4018 addiu t0,t0,16408
a8000000211c4010: 01800008 jr t0
a8000000211c4014: 00000000 nop
a8000000211c4018: 400c6000 mfc0 t0,$12
a8000000211c401c: 3c0d1000 lui t1,0x1000
a8000000211c4020: 35ad001f ori t1,t1,0x1f
a8000000211c4024: 018d6025 or t0,t0,t1
a8000000211c4028: 398c001f xori t0,t0,0x1f
a8000000211c402c: 408c6000 mtc0 t0,$12
a8000000211c4030: 3c1c211c lui gp,0x211c
a8000000211c4034: 279c0000 addiu gp,gp,0
a8000000211c4038: 679d3fe0 daddiu sp,gp,16352
a8000000211c403c: 8f8c0060 lw t0,96(gp)
Erik J. Green