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Re: CVS Update@-mips.org: linux

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: CVS Update@-mips.org: linux
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 4 Apr 2003 00:55:26 +0200
Cc: Dominic Sweetman <dom@mips.com>, linux-mips@linux-mips.org
In-reply-to: <Pine.GSO.3.96.1030403183957.19058J-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Thu, Apr 03, 2003 at 06:47:21PM +0200
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References: <16012.25072.379410.787234@gladsmuir.mips.com> <Pine.GSO.3.96.1030403183957.19058J-100000@delta.ds2.pg.gda.pl>
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On Thu, Apr 03, 2003 at 06:47:21PM +0200, Maciej W. Rozycki wrote:

> > The length of the burst is encoded in the bus command sent out by the
> > R4000 at the beginning of a read or write cycle.  For the system to
> > work, the memory controller has to be able to do the right thing for
> > both of the lengths which might happen...
> [...]
> > This is true: for L2-equipped chips I assume you can't see the
> > difference between I- and D-.
> 
>  Ah sure -- now I see where a fault in my consideration is.  While
> thinking of SC chips, I forgot of the existence of PC ones -- certainly if
> the Magnum used a PC configuration, its chipset could easily observe a
> change of a p-cache line size.

The Magum was using a PC processor.  There also was some server version of
the system based on the SC CPU but afair it was sold as Millenium 4000
but aside of the CPU it was essentially the same.

  Ralf

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