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Re: CVS Update@-mips.org: linux

To: Dominic Sweetman <dom@mips.com>
Subject: Re: CVS Update@-mips.org: linux
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Thu, 3 Apr 2003 18:47:21 +0200 (MET DST)
Cc: Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org
In-reply-to: <16012.25072.379410.787234@gladsmuir.mips.com>
Organization: Technical University of Gdansk
Original-recipient: rfc822;linux-mips@linux-mips.org
Sender: linux-mips-bounce@linux-mips.org
On Thu, 3 Apr 2003, Dominic Sweetman wrote:

> The length of the burst is encoded in the bus command sent out by the
> R4000 at the beginning of a read or write cycle.  For the system to
> work, the memory controller has to be able to do the right thing for
> both of the lengths which might happen...
[...]
> This is true: for L2-equipped chips I assume you can't see the
> difference between I- and D-.

 Ah sure -- now I see where a fault in my consideration is.  While
thinking of SC chips, I forgot of the existence of PC ones -- certainly if
the Magnum used a PC configuration, its chipset could easily observe a
change of a p-cache line size.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +


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